• 208 B transistors !!

    From mitchalsup@mitchalsup@aol.com (MitchAlsup1) to comp.arch on Thu Apr 18 19:41:09 2024
    From Newsgroup: comp.arch

    https://youtube.com/shorts/x5aiu7BTi7E?si=0knTN4-yUVOXSEsy
    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From EricP@ThatWouldBeTelling@thevillage.com to comp.arch on Thu Apr 18 17:47:17 2024
    From Newsgroup: comp.arch

    MitchAlsup1 wrote:
    https://youtube.com/shorts/x5aiu7BTi7E?si=0knTN4-yUVOXSEsy

    A quicky search finds the current EUV maximum reticle size is
    about 26 mm by 33 mm or 858 mm² (~1 inch by 1.25 inch).

    That chip sure looks bigger than that.

    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From mitchalsup@mitchalsup@aol.com (MitchAlsup1) to comp.arch on Thu Apr 18 22:41:01 2024
    From Newsgroup: comp.arch

    EricP wrote:

    MitchAlsup1 wrote:
    https://youtube.com/shorts/x5aiu7BTi7E?si=0knTN4-yUVOXSEsy

    A quicky search finds the current EUV maximum reticle size is
    about 26 mm by 33 mm or 858 mm² (~1 inch by 1.25 inch).

    That chip sure looks bigger than that.



    It looks to me about 4× that reticle limit.

    In the early 1980s someone (Amdahl?) was working on wafer scale
    lithography, apparently we have now arrived.....
    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From EricP@ThatWouldBeTelling@thevillage.com to comp.arch on Thu Apr 18 19:29:58 2024
    From Newsgroup: comp.arch

    MitchAlsup1 wrote:
    EricP wrote:

    MitchAlsup1 wrote:
    https://youtube.com/shorts/x5aiu7BTi7E?si=0knTN4-yUVOXSEsy

    A quicky search finds the current EUV maximum reticle size is
    about 26 mm by 33 mm or 858 mm² (~1 inch by 1.25 inch).

    That chip sure looks bigger than that.

    It looks to me about 4× that reticle limit.

    In the early 1980s someone (Amdahl?) was working on wafer scale
    lithography, apparently we have now arrived.....

    As part of a sales deal, in 1981 my then employer rented me and
    another guy for on-site support to Trilogy Systems,
    Amdahl's then attempt to build wafer scale IBM 370 compatibles.
    I got to live in sunny Palo Alto all expense paid for 6 months.

    Trilogy were building it with ECL macro cells on 3" wafers
    with interconnect wires patterned between 0.25" * 0.25" reticles,
    trimmed down to a single chip about 2.5" by 2.5" afterwards.

    Part of it was inventing a way to dissipate 1200 watts from
    the above chips, using liquid freon IIRC.

    Also there was no software CAD tools then so all that had to be
    invented from scratch too.

    They burned through $250 million in seed capital (DEC was one investor)
    and closed, merged into Elxsi according to Wikipedia.





    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From mitchalsup@mitchalsup@aol.com (MitchAlsup1) to comp.arch on Fri Apr 19 00:24:16 2024
    From Newsgroup: comp.arch

    EricP wrote:

    MitchAlsup1 wrote:
    EricP wrote:

    MitchAlsup1 wrote:
    https://youtube.com/shorts/x5aiu7BTi7E?si=0knTN4-yUVOXSEsy

    A quicky search finds the current EUV maximum reticle size is
    about 26 mm by 33 mm or 858 mm² (~1 inch by 1.25 inch).

    That chip sure looks bigger than that.

    It looks to me about 4× that reticle limit.

    In the early 1980s someone (Amdahl?) was working on wafer scale
    lithography, apparently we have now arrived.....

    As part of a sales deal, in 1981 my then employer rented me and
    another guy for on-site support to Trilogy Systems,
    Amdahl's then attempt to build wafer scale IBM 370 compatibles.
    I got to live in sunny Palo Alto all expense paid for 6 months.

    I really enjoyed my time in "the valley" for the 18 months I was there.
    All expenses paid would have been a goodly bonus situation.

    Trilogy were building it with ECL macro cells on 3" wafers
    with interconnect wires patterned between 0.25" * 0.25" reticles,
    trimmed down to a single chip about 2.5" by 2.5" afterwards.

    Part of it was inventing a way to dissipate 1200 watts from
    the above chips, using liquid freon IIRC.

    Imagine how quickly a 1 oz hunk of silicon would get hot at 1200 Watts
    of input power.

    Also there was no software CAD tools then so all that had to be
    invented from scratch too.

    They burned through $250 million in seed capital (DEC was one investor)
    and closed, merged into Elxsi according to Wikipedia.

    There have been similarly large expenditures in AI chips over the last decade.....to mostly naught.
    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From scott@scott@slp53.sl.home (Scott Lurndal) to comp.arch on Fri Apr 19 01:08:28 2024
    From Newsgroup: comp.arch

    mitchalsup@aol.com (MitchAlsup1) writes:
    EricP wrote:

    MitchAlsup1 wrote:
    https://youtube.com/shorts/x5aiu7BTi7E?si=0knTN4-yUVOXSEsy

    A quicky search finds the current EUV maximum reticle size is
    about 26 mm by 33 mm or 858 mm² (~1 inch by 1.25 inch).

    That chip sure looks bigger than that.



    It looks to me about 4× that reticle limit.

    In the early 1980s someone (Amdahl?) was working on wafer scale
    lithography, apparently we have now arrived.....


    Cerebras has a wafer-scale chip in production.

    Self healing, and works around defects.

    The CS-3 has 900,000 cores and 44GB on-chip memory.

    https://www.cerebras.net/
    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From scott@scott@slp53.sl.home (Scott Lurndal) to comp.arch on Fri Apr 19 01:11:02 2024
    From Newsgroup: comp.arch

    mitchalsup@aol.com (MitchAlsup1) writes:
    EricP wrote:

    MitchAlsup1 wrote:
    EricP wrote:

    MitchAlsup1 wrote:
    https://youtube.com/shorts/x5aiu7BTi7E?si=0knTN4-yUVOXSEsy

    A quicky search finds the current EUV maximum reticle size is
    about 26 mm by 33 mm or 858 mm² (~1 inch by 1.25 inch).

    That chip sure looks bigger than that.

    It looks to me about 4× that reticle limit.

    In the early 1980s someone (Amdahl?) was working on wafer scale
    lithography, apparently we have now arrived.....

    As part of a sales deal, in 1981 my then employer rented me and
    another guy for on-site support to Trilogy Systems,
    Amdahl's then attempt to build wafer scale IBM 370 compatibles.
    I got to live in sunny Palo Alto all expense paid for 6 months.

    I really enjoyed my time in "the valley" for the 18 months I was there.
    All expenses paid would have been a goodly bonus situation.

    I've lived and worked there for thirty five years now. Just got
    back from a hike in a nearby redwood forest.

    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From John Savard@quadibloc@servername.invalid to comp.arch on Sat Apr 20 22:28:41 2024
    From Newsgroup: comp.arch

    On Thu, 18 Apr 2024 22:41:01 +0000, mitchalsup@aol.com (MitchAlsup1)
    wrote:

    In the early 1980s someone (Amdahl?) was working on wafer scale
    lithography, apparently we have now arrived.....

    Actually, several companies were. The one mentioned, Trilogy, was the
    one that spun off of Amdahl. There was also the company that was going
    to make the solid state storage wafer for the Sinclair, the name of
    which was Anamartic. Texas Instruments and ITT also researched its possibilities.

    John Savard
    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From BGB@cr88192@gmail.com to comp.arch on Sun Apr 21 14:10:06 2024
    From Newsgroup: comp.arch

    On 4/20/2024 11:28 PM, John Savard wrote:
    On Thu, 18 Apr 2024 22:41:01 +0000, mitchalsup@aol.com (MitchAlsup1)
    wrote:

    In the early 1980s someone (Amdahl?) was working on wafer scale
    lithography, apparently we have now arrived.....

    Actually, several companies were. The one mentioned, Trilogy, was the
    one that spun off of Amdahl. There was also the company that was going
    to make the solid state storage wafer for the Sinclair, the name of
    which was Anamartic. Texas Instruments and ITT also researched its possibilities.


    On the other side of things, I am wondering what sorts of densities and
    clock speeds are possible with printed electronics on a plastic
    substrate (such as PET).

    Information on the subject is fairly sparse, but inks seem to be
    available (albeit expensive), albeit with some variation as to printer technology. Seems to be be either organic or inorganic inks, with
    inkjet, offset, and screen printing, as the main variations in printer technology (with different inks for the different methods).



    Though, I will assume that by inkjet, they don't mean just using a
    repurposed consumer-grade printer (possibly with the ROM's hacked to
    allow them to use refilled ink cartridges, with the non-standard inks).

    Then again, with these things, they have created a situation where there
    are a lot of old inkjet printers around, mostly because it is often
    cheaper to buy a whole new printer than to buy the ink refill cartridges
    for said printer (vs, say, laser printers where the printer is more
    expensive, but the toner refills are more reasonable).

    Looking around, it seems some people are instead using the more "office
    style" inkjet printers for this (which apparently allow for refilling
    the ink cartridges).


    Also seems the N and P doped inks are rarer and more expensive than the conductive metallic and insulator inks.

    No information on what sorts of densities are possible; crude guess is
    it is roughly a ~ 133333um process, based on the assumption of a 300 dpi printer (possibly more or less).

    If one assumes, say, 6-dots width for a transistor, this would be ~
    50x50 transistors per square inch, or possibly ~ 200k transistors per
    page...

    I guess, if one could get it to run at MHz speeds, this could be enough
    for a CPU.

    Though, would likely need multiple passes through the printer to print something like this, say:
    Print transistor layers;
    Bake the sheet;
    Print insulator and metal trace layers;
    Bake;
    Print more insulator and metal trace layers;
    Bake;
    ...

    Possibly, a person could also print vias and then do multiple layers of transistors per page, possibly up to some set limit.


    Not entirely sure how one would go about mapping digital logic onto
    printable layers though. This may well be the hard part.

    I will make a guess that there are probably no Verilog to semiconductive-ink-PNG compilers.


    ...


    John Savard

    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From mitchalsup@mitchalsup@aol.com (MitchAlsup1) to comp.arch on Sun Apr 21 22:02:34 2024
    From Newsgroup: comp.arch

    BGB wrote:

    On 4/20/2024 11:28 PM, John Savard wrote:
    On Thu, 18 Apr 2024 22:41:01 +0000, mitchalsup@aol.com (MitchAlsup1)
    wrote:

    In the early 1980s someone (Amdahl?) was working on wafer scale
    lithography, apparently we have now arrived.....

    Actually, several companies were. The one mentioned, Trilogy, was the
    one that spun off of Amdahl. There was also the company that was going
    to make the solid state storage wafer for the Sinclair, the name of
    which was Anamartic. Texas Instruments and ITT also researched its
    possibilities.


    On the other side of things, I am wondering what sorts of densities and clock speeds are possible with printed electronics on a plastic
    substrate (such as PET).

    Information on the subject is fairly sparse, but inks seem to be
    available (albeit expensive), albeit with some variation as to printer technology. Seems to be be either organic or inorganic inks, with
    inkjet, offset, and screen printing, as the main variations in printer technology (with different inks for the different methods).

    To determine wire delay per unit length, one would need the LRC values
    of the conductor and insulators. Copper on Epoxy allows for transmission
    speeds of ½ that of light, and I think you would be resistance limited.

    So, we need:: 1) Ohms per square, 2) inductance per unit length, and
    3) capacitance per unit area.

    Though, I will assume that by inkjet, they don't mean just using a repurposed consumer-grade printer (possibly with the ROM's hacked to
    allow them to use refilled ink cartridges, with the non-standard inks).

    Then again, with these things, they have created a situation where there
    are a lot of old inkjet printers around, mostly because it is often
    cheaper to buy a whole new printer than to buy the ink refill cartridges
    for said printer (vs, say, laser printers where the printer is more expensive, but the toner refills are more reasonable).

    Looking around, it seems some people are instead using the more "office style" inkjet printers for this (which apparently allow for refilling
    the ink cartridges).


    Also seems the N and P doped inks are rarer and more expensive than the conductive metallic and insulator inks.

    No information on what sorts of densities are possible; crude guess is
    it is roughly a ~ 133333um process, based on the assumption of a 300 dpi printer (possibly more or less).

    300 DPI is 1995 technology, I would be surprised if you could not find
    4800 DPI printers. This, alone, changes the lambda by 160×.

    If one assumes, say, 6-dots width for a transistor, this would be ~
    50x50 transistors per square inch, or possibly ~ 200k transistors per page...

    Generally, the planar technologies had 6 lambda (min) source and drains
    with 4 Lambda gates and one would need 9 lambda to drop a contact on
    a source or drain. So, a minimum contacted transistor would be 9+4+9
    = 22 lambda wide. Generally one wanted 4 lambda between different
    active regions, to the pitch of this minimum contacted transistor would
    be 9+4 = 13 lambda.

    I guess, if one could get it to run at MHz speeds, this could be enough
    for a CPU.

    Though, would likely need multiple passes through the printer to print something like this, say:
    Print transistor layers;
    Bake the sheet;
    Print insulator and metal trace layers;
    Bake;
    Print more insulator and metal trace layers;
    Bake;
    ...

    Your typical 2 layer metal CMOS process in 1.5µ had 200 steps in it.
    1) spin on resist
    2) bake resist
    3) expose resist (mask 1: P-wells and N-well contacts)
    4) develop resist
    5) etch resist
    6) clean wafer
    7) ion-implant exposed wafer
    8) clean wafer

    8 similar steps for N-wells

    17) deposit polysilicon
    18) bake polysilicon
    19) spin on resist
    20) bake resist
    21) expose resist
    22) develop resist
    23) etch resist
    24) clean wafer

    25) spin on resist
    26) bake resist
    27) expose resist (P-Channel)
    28) develop resist
    29) etch resist
    30) clean wafer
    31) P-channel implants (arsenic)

    32) spin on resist
    33) bake resist
    34) expose resist (N-Channel)
    35) develop resist
    36) etch resist
    37) clean wafer
    38) N-channel implants (phosphorous)

    Then, for each contact layer one has 8 steps, and for each metal layer
    one would have 10 steps. Then a thick passivation, then cutting of the
    bonding pads, and finally, a back lap of the wafer to clean contaminates
    and a 3 atom thick gold sputter so one can solder the Si die to the
    package.

    So, the problem becomes one of how does one get the pads attached to
    the "other" components in the system ??

    Possibly, a person could also print vias and then do multiple layers of transistors per page, possibly up to some set limit.


    Not entirely sure how one would go about mapping digital logic onto printable layers though. This may well be the hard part.

    Straightforward place and route.

    I will make a guess that there are probably no Verilog to semiconductive-ink-PNG compilers.


    ....


    John Savard
    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From BGB@cr88192@gmail.com to comp.arch on Sun Apr 21 19:02:55 2024
    From Newsgroup: comp.arch

    On 4/21/2024 5:02 PM, MitchAlsup1 wrote:
    BGB wrote:

    On 4/20/2024 11:28 PM, John Savard wrote:
    On Thu, 18 Apr 2024 22:41:01 +0000, mitchalsup@aol.com (MitchAlsup1)
    wrote:

    In the early 1980s someone (Amdahl?) was working on wafer scale
    lithography, apparently we have now arrived.....

    Actually, several companies were. The one mentioned, Trilogy, was the
    one that spun off of Amdahl. There was also the company that was going
    to make the solid state storage wafer for the Sinclair, the name of
    which was Anamartic. Texas Instruments and ITT also researched its
    possibilities.


    On the other side of things, I am wondering what sorts of densities
    and clock speeds are possible with printed electronics on a plastic
    substrate (such as PET).

    Information on the subject is fairly sparse, but inks seem to be
    available (albeit expensive), albeit with some variation as to printer
    technology. Seems to be be either organic or inorganic inks, with
    inkjet, offset, and screen printing, as the main variations in printer
    technology (with different inks for the different methods).

    To determine wire delay per unit length, one would need the LRC values
    of the conductor and insulators. Copper on Epoxy allows for transmission speeds of ½ that of light, and I think you would be resistance limited.

    So, we need:: 1) Ohms per square, 2) inductance per unit length, and 3) capacitance per unit area.


    Dunno there...

    It looks like a lot of the metallic inks are silver or copper based.

    Not entirely sure how it works. Apparently one needs to bake the sheet
    for the components in the ink to turn into their final forms, but around 80-120C is well below the melting points of silver or copper (but, they apparently somehow sinter at these temperatures).


    Would need to have an oven that does accurate temperature control, since
    if part doesn't get hot enough, the ink wont set correctly, and if too
    hot, the PET substrate might warp or melt, ...


    Though, I will assume that by inkjet, they don't mean just using a
    repurposed consumer-grade printer (possibly with the ROM's hacked to
    allow them to use refilled ink cartridges, with the non-standard inks).

    Then again, with these things, they have created a situation where
    there are a lot of old inkjet printers around, mostly because it is
    often cheaper to buy a whole new printer than to buy the ink refill
    cartridges for said printer (vs, say, laser printers where the printer
    is more expensive, but the toner refills are more reasonable).

    Looking around, it seems some people are instead using the more
    "office style" inkjet printers for this (which apparently allow for
    refilling the ink cartridges).


    Also seems the N and P doped inks are rarer and more expensive than
    the conductive metallic and insulator inks.

    No information on what sorts of densities are possible; crude guess is
    it is roughly a ~ 133333um process, based on the assumption of a 300
    dpi printer (possibly more or less).

    300 DPI is 1995 technology, I would be surprised if you could not find
    4800 DPI printers. This, alone, changes the lambda by 160×.


    The stuff I was aware of, printer resolution was usually assumed to be
    between 72 to 300 DPI.

    Apparently (looks up stuff), inkjet typically ranges from 300 to 720 DPI
    (with 600 to 1200 for laser printers, and 1000 to 2400 for photo printers).


    Not sure of the DPI of a generic office-style inkjet printer (assuming
    one gets one of the ones that allows for refillable ink cartridges).



    If one assumes, say, 6-dots width for a transistor, this would be ~
    50x50 transistors per square inch, or possibly ~ 200k transistors per
    page...

    Generally, the planar technologies had 6 lambda (min) source and drains
    with 4 Lambda gates and one would need 9 lambda to drop a contact on
    a source or drain. So, a minimum contacted transistor would be 9+4+9
    = 22 lambda wide. Generally one wanted 4 lambda between different active regions, to the pitch of this minimum contacted transistor would
    be 9+4 = 13 lambda.


    OK.

    So, I guess similar would hold if one had a 1200 DPI printer...

    But, only 50k for 600 DPI.

    Seems like this could handle a lot of 8/16 era CPUs on a sheet.

    Though, saw a video talking about it, and they had a printed Cortex-M0
    on a smaller piece of plastic (around 4in^2 IIRC), but the video didn't
    say what sort of printer or inks they were using, so...


    I guess, if one could get it to run at MHz speeds, this could be
    enough for a CPU.

    Though, would likely need multiple passes through the printer to print
    something like this, say:
       Print transistor layers;
       Bake the sheet;
       Print insulator and metal trace layers;
       Bake;
       Print more insulator and metal trace layers;
       Bake;
       ...

    Your typical 2 layer metal CMOS process in 1.5µ had 200 steps in it.
    1) spin on resist
    2) bake resist 3) expose resist (mask 1: P-wells and N-well contacts)
    4) develop resist
    5) etch resist
    6) clean wafer
    7) ion-implant exposed wafer
    8) clean wafer

    8 similar steps for N-wells

    17) deposit polysilicon
    18) bake polysilicon
    19) spin on resist
    20) bake resist
    21) expose resist
    22) develop resist
    23) etch resist
    24) clean wafer

    25) spin on resist
    26) bake resist
    27) expose resist (P-Channel)
    28) develop resist
    29) etch resist
    30) clean wafer
    31) P-channel implants (arsenic)

    32) spin on resist
    33) bake resist
    34) expose resist (N-Channel)
    35) develop resist
    36) etch resist
    37) clean wafer
    38) N-channel implants (phosphorous)

    Then, for each contact layer one has 8 steps, and for each metal layer
    one would have 10 steps. Then a thick passivation, then cutting of the bonding pads, and finally, a back lap of the wafer to clean contaminates
    and a 3 atom thick gold sputter so one can solder the Si die to the
    package.

    So, the problem becomes one of how does one get the pads attached to
    the "other" components in the system ??


    I am guessing the process for inkjet on a plastic substrate is somewhat different from that used for optical lithography on silicon.

    But, the information I had seen implies it is mostly printing onto the
    sheet, and then baking the sheet so that all the components sinter
    together, then more printing, and more baking, for each layer.

    Well, unless it is print/dry/print/dry, with baking as a final step
    (where dry is done at a lower temperature than bake).


    Also not obvious which of the various types of ink one would use, etc...



    Possibly, a person could also print vias and then do multiple layers
    of transistors per page, possibly up to some set limit.


    Not entirely sure how one would go about mapping digital logic onto
    printable layers though. This may well be the hard part.

    Straightforward place and route.


    There is a pretty big gap between Verilog and the actual transistors.
    But, yeah, in concept, probably some way to compile Verilog to a
    netlist, and then to convert the netlist to the various component layers.


    I will make a guess that there are probably no Verilog to
    semiconductive-ink-PNG compilers.


    Though, probably actually TIFF, as one needs a format that can hopefully specify things in terms of the CMYK system, so that hopefully it prints
    stuff with the correct inks, rather than blending them all together...



    ....


    John Savard

    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From Terje Mathisen@terje.mathisen@tmsw.no to comp.arch on Mon Apr 22 08:08:31 2024
    From Newsgroup: comp.arch

    BGB wrote:
    On 4/21/2024 5:02 PM, MitchAlsup1 wrote:
    BGB wrote:

    No information on what sorts of densities are possible; crude guess
    is it is roughly a ~ 133333um process, based on the assumption of a
    300 dpi printer (possibly more or less).

    300 DPI is 1995 technology, I would be surprised if you could not find>> 4800 DPI printers. This, alone, changes the lambda by 160×.


    The stuff I was aware of, printer resolution was usually assumed to be > between 72 to 300 DPI.

    Apparently (looks up stuff), inkjet typically ranges from 300 to 720 DPI (with 600 to 1200 for laser printers, and 1000 to 2400 for photo printers).


    Not sure of the DPI of a generic office-style inkjet printer (assuming > one gets one of the ones that allows for refillable ink cartridges).
    I probably do more high-resolution printing than most of you, since I'm
    the leader of the Mapping Commision of the Norwegian Orienteering
    Federation.
    For any given orienteering map, we need to print very sharp (i.e.
    maximum contrast) lines. Both black (road edges etc) and brown
    (contours) lines are just 0.10mm wide, and since brown requires a CMYK
    mix of either 3 or 4 components, you have to start with a _very_ high resolution printer to consistently get good results.
    2400x2400 DPI is what you really need, it is available on the highest
    end print engines (from Xerox and others), but you also need very good software to generate visually optimal vector to raster conversions (i.e. like the industry standard Fiery RIP).
    1200x1200 laser printers are the new medium/low end standard, you can
    get that with A3 size paper at a reasonable price.
    Ink jet photo printers typically deliver significantly smaller dot
    sizes, but at far higher per page costs.
    Terje
    --
    - <Terje.Mathisen at tmsw.no>
    "almost all programming can be viewed as an exercise in caching"
    --- Synchronet 3.20a-Linux NewsLink 1.114
  • From BGB@cr88192@gmail.com to comp.arch on Mon Apr 22 03:26:39 2024
    From Newsgroup: comp.arch

    On 4/22/2024 1:08 AM, Terje Mathisen wrote:
    BGB wrote:
    On 4/21/2024 5:02 PM, MitchAlsup1 wrote:
    BGB wrote:

    No information on what sorts of densities are possible; crude guess
    is it is roughly a ~ 133333um process, based on the assumption of a
    300 dpi printer (possibly more or less).

    300 DPI is 1995 technology, I would be surprised if you could not find
    4800 DPI printers. This, alone, changes the lambda by 160×.


    The stuff I was aware of, printer resolution was usually assumed to be
    between 72 to 300 DPI.

    Apparently (looks up stuff), inkjet typically ranges from 300 to 720
    DPI (with 600 to 1200 for laser printers, and 1000 to 2400 for photo
    printers).


    Not sure of the DPI of a generic office-style inkjet printer (assuming
    one gets one of the ones that allows for refillable ink cartridges).

    I probably do more high-resolution printing than most of you, since I'm
    the leader of the Mapping Commision of the Norwegian Orienteering Federation.

    For any given orienteering map, we need to print very sharp (i.e.
    maximum contrast) lines. Both black (road edges etc) and brown
    (contours) lines are just 0.10mm wide, and since brown requires a CMYK
    mix of either 3 or 4 components, you have to start with a _very_ high resolution printer to consistently get good results.

    2400x2400 DPI is what you really need, it is available on the highest
    end print engines (from Xerox and others), but you also need very good software to generate visually optimal vector to raster conversions (i.e. like the industry standard Fiery RIP).

    1200x1200 laser printers are the new medium/low end standard, you can
    get that with A3 size paper at a reasonable price.

    Ink jet photo printers typically deliver significantly smaller dot
    sizes, but at far higher per page costs.


    For printing on paper, yeah, laser printers make sense, and that is what
    I am using here...



    But, it seems most of the printable electronics stuff, is using inkjet-printable inks rather than toner.

    I had looked into it more, and it seems that most of this stuff was
    built around PMOS logic.



    Looks like one of the dominant inks in this area is PEDOT:PSS, eg: https://en.wikipedia.org/wiki/PEDOT:PSS

    Things like N-channel inks apparently exist, but are less readily available.


    So, this likely this means one would need 3 inks:
    copper or silver metallic ink;
    insulator/dialectic ink;
    something like PEDOT:PSS.

    With transistors formed by layering these on top of each other, say:
    Source and Drain traces;
    P-Channel;
    Insulator;
    Gate trace.

    Say, making sure to print down layers of insulator wherever one does not
    want traces to touch.


    I guess, in the off chance I bought any of this stuff, might make sense
    to first experiment with trying to get traces and basic transistors to
    work, since probably getting digital logic mapped to this is going to be difficult (doesn't seem like there are many existing FOSS tools for this
    sort of thing).


    Though, I guess, if one can make it look sort of like an FPGA, it is conceivably possible one could use Yosys or similar for the front-end
    Verilog compiler.

    Say, one can try to map every possible LUT4 to a predefined pattern, and
    then generate a netlist of mostly LUT4's and FF's and similar (similar
    to an ICE40 or ECP5). Effectively treating the page like it were an
    FPGA. Actual place/route could drop down pre-drawn blocks of pixels, and
    then figure out a pattern for the routing layers.


    Also seems like the relevant type of printers are more in the $200-$500
    range (eg: high DPI and refillable), rather than the cheaper $30-$60 models.


    Terje


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