From Newsgroup: comp.arch
"Chris M. Thomasson" <
chris.m.thomasson.1@gmail.com> posted:
We sure have atomic RMW for compute shaders, heck...
Even CAS! :^)
But do any shader languages or GPU architectures expose a true LL/SC?
Not that I know of::
Shader kernels run multiple threads simultaneously, so when the LL*
instruction comes up, 32 threads attempt the "get" and if any of the
addresses are the same, SC will fail continuously. Therefore, their
model is that of memory-atomics (i.e., RMW) so all threads from all
warps make forward progress without regards to the timing of individual
warps or threads.
(*) which is why they would not have an LL (or SC) instruction. Whereas
CPUs would allow 1 thread to make forward progress at least some of the
time.
Op-to-memory returning the previous value can be performed at modest
overhead compared to (cache miss) memory-latency.
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