So how about a circuit board where the traces are made of liquid metal
that can be made to reflow into new configurations? This way, the
board can be configured into an entirely different circuit in less
than a minute <https://www.tomshardware.com/tech-industry/prototype-of-the-worlds-first-fluid-circuit-board-can-be-physically-rewired-in-less-than-a-minute-startup-claims-could-make-hardware-iteration-1-000-times-faster-than-traditional-pcb>.
Did Xilinx have some kind of reconfigurable gate system? As I recall,
you had to reload the gate configuration into the chip every time it
was powered up.
Lawrence =?iso-8859-13?q?D=FFOliveiro?= <ldo@nz.invalid> posted:
So how about a circuit board where the traces are made of liquid metal
that can be made to reflow into new configurations? This way, the
board can be configured into an entirely different circuit in less
than a minute
<https://www.tomshardware.com/tech-industry/prototype-of-the-worlds-first-fluid-circuit-board-can-be-physically-rewired-in-less-than-a-minute-startup-claims-could-make-hardware-iteration-1-000-times-faster-than-traditional-pcb>.
Did Xilinx have some kind of reconfigurable gate system? As I recall,
you had to reload the gate configuration into the chip every time it
was powered up.
Get this to work at the 10nm level and we change FPGAs into recompilable Standard Cells.
When CPUs have certain things "fused off" either because they didn't
work or for market segmentation, could the same technique be used
for one time programmability on a fine level?
MitchAlsup <user5857@newsgrouper.org.invalid> writes:
Lawrence =?iso-8859-13?q?D=FFOliveiro?= <ldo@nz.invalid> posted:
So how about a circuit board where the traces are made of liquid metal
that can be made to reflow into new configurations? This way, the
board can be configured into an entirely different circuit in less
than a minute
<https://www.tomshardware.com/tech-industry/prototype-of-the-worlds-first-fluid-circuit-board-can-be-physically-rewired-in-less-than-a-minute-startup-claims-could-make-hardware-iteration-1-000-times-faster-than-traditional-pcb>.
Did Xilinx have some kind of reconfigurable gate system? As I recall,
you had to reload the gate configuration into the chip every time it
was powered up.
Get this to work at the 10nm level and we change FPGAs into recompilable
Standard Cells.
When CPUs have certain things "fused off" either because they didn't
work or for market segmentation, could the same technique be used for
one time programmability on a fine level?
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