From Newsgroup: comp.arch

I didn't have a way to contact Mitch directly, so I'm posting this here
I was wondering if you were involved at all in the development of the 88110
and if you knew anything about the early development history, particularly Apple and NeXT's involvement.

I was part of Hugh Martin's RISC Projects group at Apple, but started about
a year after the project got under way. The earliest document on the CPU
that I have is http://bitsavers.org/pdf/apple/risc_products/jaguar/Jaguar_Architecture_Rev2.0_XJS_88110_19890330.pdf

Hugh Martin, John Sell, Ron Hochsprung, and Toby Farrand would have been involved on Apple's side.

Sadly, we never received a fully working 88110 part before the PPC deal happened.
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From Newsgroup: comp.arch


Al Kossow <aek@bitsavers.org> posted:

I didn't have a way to contact Mitch directly, so I'm posting this here
I was wondering if you were involved at all in the development of the 88110 and if you knew anything about the early development history, particularly Apple and NeXT's involvement.

Only on a cursorily basis.

I was part of Hugh Martin's RISC Projects group at Apple, but started about
a year after the project got under way. The earliest document on the CPU
that I have is http://bitsavers.org/pdf/apple/risc_products/jaguar/Jaguar_Architecture_Rev2.0_XJS_88110_19890330.pdf

The question in my mind was always:: "Why did Apple demand 80-bit FP for
88110 and then drop that demand when IBM said no on PPC" ???

80-bit FP put the whole effort back about 6-months--and we did tell you
so.

Hugh Martin, John Sell, Ron Hochsprung, and Toby Farrand would have been involved on Apple's side.

Sadly, we never received a fully working 88110 part before the PPC deal happened.

A deal that left everyone wondering .....
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From Newsgroup: comp.arch

MitchAlsup <user5857@newsgrouper.org.invalid> writes:

Al Kossow <aek@bitsavers.org> posted:

I didn't have a way to contact Mitch directly, so I'm posting this here
I was wondering if you were involved at all in the development of the 88110 >> and if you knew anything about the early development history, particularly >> Apple and NeXT's involvement.

Only on a cursorily basis.

I was part of Hugh Martin's RISC Projects group at Apple, but started about >> a year after the project got under way. The earliest document on the CPU
that I have is http://bitsavers.org/pdf/apple/risc_products/jaguar/Jaguar_Architecture_Rev2.0_XJS_88110_19890330.pdf

The question in my mind was always:: "Why did Apple demand 80-bit FP for >88110 and then drop that demand when IBM said no on PPC" ???

80-bit FP put the whole effort back about 6-months--and we did tell you
so.

Hugh Martin, John Sell, Ron Hochsprung, and Toby Farrand would have been
involved on Apple's side.

Sadly, we never received a fully working 88110 part before the PPC deal happened.

A deal that left everyone wondering .....

At Unisys, we had shipped systems using the 88000 and were designing
what became the SPP (Scalable Parallel Processor) massivly parallel
system based on the 88110. Its cancellation caused a mad scramble
to evaluate all the other extant RISC processors (Sparc, MIPS, PPC);
for various reasons we settled on the Pentium Pro (P6) and the system
shipped with 200Mhz P6 processors (up to 64 per system).

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From Newsgroup: comp.arch

On 9/27/25 9:41 AM, MitchAlsup wrote:

The question in my mind was always:: "Why did Apple demand 80-bit FP for 88110 and then drop that demand when IBM said no on PPC" ???

Compatibility with Apple's SANE floating-point package.

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From Newsgroup: comp.arch


Al Kossow <aek@bitsavers.org> posted:

On 9/27/25 9:41 AM, MitchAlsup wrote:

The question in my mind was always:: "Why did Apple demand 80-bit FP for 88110 and then drop that demand when IBM said no on PPC" ???

Compatibility with Apple's SANE floating-point package.

Yes, but then why did they drop said "requirement" the instant
IBM came on board ?!?
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From Newsgroup: comp.arch

On 9/27/25 11:49 AM, MitchAlsup wrote:

Yes, but then why did they drop said "requirement" the instant
IBM came on board ?!?

I was in a few of the IBM/Apple meetings. It was decided SANE
compatibility would just be emulated to get 601 out the door.
I was outvoted on keeping an independent clock on the time base
register for 603/604 like the 601 had.


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From Newsgroup: comp.arch

scott@slp53.sl.home (Scott Lurndal) writes:

At Unisys, we had shipped systems using the 88000 and were designing
what became the SPP (Scalable Parallel Processor) massivly parallel
system based on the 88110. Its cancellation caused a mad scramble
to evaluate all the other extant RISC processors (Sparc, MIPS, PPC);
for various reasons we settled on the Pentium Pro (P6) and the system
shipped with 200Mhz P6 processors (up to 64 per system).

Data General also switched from 88K to the Pentium Pro.

- anton

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From Newsgroup: comp.arch

On Sat, 27 Sep 2025 21:29:58 GMT, M. Anton Ertl wrote:

Data General also switched from 88K to the Pentium Pro.

The Pentium Pro was the one that gave great 32-bit performance, but
sacrificed 16-bit performance. Because Intel assumed that 16-bit code
would be on the way out by that point.

The DOS/Windows world said otherwise ...
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From Newsgroup: comp.arch

Lawrence D’Oliveiro [2025-09-28 00:23:26] wrote:

On Sat, 27 Sep 2025 21:29:58 GMT, M. Anton Ertl wrote:

Data General also switched from 88K to the Pentium Pro.

The Pentium Pro was the one that gave great 32-bit performance, but sacrificed 16-bit performance. Because Intel assumed that 16-bit code
would be on the way out by that point.
The DOS/Windows world said otherwise ...

Did it, really? I mean, from a marketing point of view you're probably
right that it suffered, but my impression is that its performance was
great even in the DOS/Windows world for most of the programs where
performance mattered. IOW, most of the programs for which its
performance was disappointing were programs where performance was not particularly important.

Admittedly, I had no first-hand experience with Windows on those CPUs
(ran Redhat on those), so maybe I just missed the real problems?


Stefan
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From Newsgroup: comp.arch

Lawrence D’Oliveiro wrote:

On Sat, 27 Sep 2025 21:29:58 GMT, M. Anton Ertl wrote:

Data General also switched from 88K to the Pentium Pro.

The Pentium Pro was the one that gave great 32-bit performance, but sacrificed 16-bit performance. Because Intel assumed that 16-bit code
would be on the way out by that point.

The DOS/Windows world said otherwise ...

That is not quite true:
Yes, the P6/PPro had a couple of snags, the most serious one was still
not really important, except it hit a number of very carefully optimized asm inner loops:
Partial Register Stalls
When you update a part of a register, like AL/AH/AX and then use a
larger part like AX/EAX, the cpu would stall until all previous
instructions had retired before the new part could be merged with the
older full register.
In my own Word Count code, which broke whatever records existed on the Pentium, counting characters/word/lines at 40 MB/s on a 60 MHz Pentium,
that fully unrolled inner loop would now suffer a PRS stall every 1 or 2 normal cycles.
Sounds really bad, except (a) word count is not a performance critical functions for any known scenario/user experience, and (b) even with the
PRS stalls, the 200 MHz PPro still ran at over 20 MB/s.
Finally, the final OoO-compatible version of my wc code had 5 or 6
different kernels and would start every run by benchmarking all of the algorithms on the first 4KB of input, then use the fastest one for the remainder.
Terje
--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"
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